Silicon Interfaces to present Low Power and Area Efficient 64 Bit Vedic Multiplier Design for High-Speed Operation in ASIC-DSP Applications

PRESS RELEASE

Silicon Interfaces^® - to present "Low Power and Area Efficient 64 Bit Vedic Multiplier Design for High-Speed Operation in ASIC-DSP Applications" at the Engineering Track Front-End Program at the landmark 60th Design Automation Conference being held at the historic and iconic Moscone West Center, San Francisco, CA, USA

Silicon Valley, CA, 7th July 2023 9:00 am

Technology has finally turned a full cycle ... What was known and computed in ancient times has finally taken the center stage and is now setting the pace for the future. And there can be no better validation than the acceptance, not only by the Technical Committee at the Design Automation Conference but widely worldwide that Vedic Mathematics had some fundamentals which may be leveraged to overcome the challenges of higher speed, lower power, and area.

The 60th DAC USA 2023 has selected the paper for a presentation with the topic "133 Low Power and Area Efficient 64-Bit Vedic Multiplier Design for High-Speed Operation in ASIC-DSP Applications."

Silicon Interfaces has been undertaking far-reaching research in areas of Cross-Platform Portability of Single Intent Test Cases with enhanced scenarios and data integrity, Low Power Methodologies within Verification Methodologies, and leveraging Artificial Intelligence and Machine Learning for Fault Simulation and for the first time forayed into the world Arithmetic Logic Units as prevalent in Cores and multi-Core. The advantages of a Vedic Multiplier have multiple cascaded effects on any processing and in many applications, like Digital signal processing, Image Processing, Cryptography, High-performance Computing, and Communications.

"No, this presentation of the Vedic Multiplier is factual and real and not a product of cosmic inductance, said Mrs. Heena Bhatia, Chief Business Officer, of Silicon Interfaces. Prof Purananda Sastry emphasized, "The first time I tried to follow the sutra, doubts crept in about its viability, but when we ran the code there has only been excitement all around".

About Silicon Interfaces

Silicon Interfaces offers specialized semiconductors and microelectronics services for Low Power Designs, Portable Stimulus Standards (PSS) for Verification, Functional Safety Assurance and Fault Simulation, SystemC TLM, Verilog, SystemVerilog and UVM, EDA tools Product Support/Validation and EDA Infrastructure tools Development in Python/Php/Qt for customers in North America, Europe and Asia Pacific. Please visit www.siliconinterfaces.com

Silicon Interfaces is a powerhouse of Intellectual Property developed by its team of Engineers. These are owned and copyrighted by Silicon Interfaces and sold as Portfolio of IPs. Silicon Interfaces released effective 2002 a plethora of 14 IPs and consequently 6+ Verification IP across a broad spectrum. The Program is targeted to the Wireless and Wired Networking, Data Communications and Inter-connect areas, with extensions to Embedded and Storage areas. The program offers a Portfolio of Design IPs and has a program for Roadmap IPs.

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